This application claims the priority of Korean patent application Ser. No. 99-61042 filed on Dec. 23, 1999.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device configured to reduce a step difference between a memory cell region and a logic circuit region adjacent thereto, thereby attaining fineness of interconnection wirings.
2. Description of the Related Art
Recently, in accordance with high integration and high performance of a semiconductor device, the cell size is gradually reduced. Accordingly, the height of a stacked capacitor provided in a semiconductor device becomes increased so as to cope with the reduced cell size and to attain a required secured capacitance.
In other words, in order to compensate for a reduction in the surface area of a dielectric corresponding to the reduced cell size, the height of a stacked capacitor is increased, resulting in a relatively large step difference between a memory cell region where the capacitor is formed, and a logic circuit region adjacent thereto.
A method of manufacturing a conventional semiconductor device will be described with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating a method of manufacturing a conventional semiconductor device.
According to the method of manufacturing a conventional semiconductor device, as shown in FIG. 1, a predetermined logic circuit is formed on a logic circuit region A on a semiconductor substrate 10, and a first etching stopper film 11 is formed on a memory cell region B by depositing nitride on the entire surface where a plurality of transistors for driving a capacitor to be formed in a subsequent process, are formed.
Then, oxide is stacked on the first etching stopper film 11 and then planarized by a chemical mechanical polishing (CMP) process, thereby forming a first interlayer insulating film 21.
Here, reference numeral 1 denotes a well of first conductivity type (e.g., an n-type), 2 denotes a well of a second conductivity type (e.g., a p-type), 3 denotes an isolation insulating layer, 4 denotes an active region used as a source electrode 4a or a drain electrode 4b, 5 denotes a gate oxide layer, 6 denotes a gate electrode, and 7 denotes an intermediate insulating film.
Subsequently, a first contact hole (not shown) exposing the drain electrode 4b in the memory cell region B is formed by partially removing the first interlayer insulating film 21 of the memory cell region B and the first etching stopper film 11.
Next, the first contact hole is filled with a conductive material (e.g., polysilicon), and then the conductive material remaining on the first interlayer insulating film 21 is removed by an etch-back process, thereby forming a first contact plug 31.
Here, the first contact plug 31 formed in the drain electrode 4b of the memory cell region B is electrically connected to a charge preservation electrode in a subsequent process.
Also, when the drain electrode 4b in the memory cell region B is exposed, the source electrode 4a may also be exposed to form a contact plug, for forming a bit line contact in the contact plug during a subsequent process.
Subsequently, oxide is deposited on the entire surface of the structure having the first contact plug 31, thereby forming a second interlayer insulating film 22.
Next, the second interlayer insulating film 22, the first interlayer insulating film 21 and the first etching stopper film 11 are partially removed in sequence, thereby forming a second contact hole exposing the source electrode 4a in the memory cell region B to be connected with a bit line during a subsequent process, the active region 4 in the logic circuit region A to be connected with a first interconnection wiring, and the surface of the gate electrode 6.
Here, in the case where a contact plug is also formed in the source electrode 4a in the above-described process, the second contact hole for a bit line is formed on the contact plug.
Then, a conductive material is deposited over the second contact hole and on the second interlayer insulating film 22 to form a first conductive layer 41a and 41b, and then an insulating material is deposited on the entire surface of the first conductive layer 41a and 41b to form a second intermediate insulating film 25.
Here, the first conductive layer is patterned in a subsequent process, so that the first conductive layer 41a remaining in the logic circuit region A is used as an interconnection wiring and the first conductive layer 41b remaining in the memory cell region B is used as a bit line.
Thereafter, the second intermediate insulating film 25, the first conductive layer 41b and the second interlayer insulating film 22 disposed under the first conductive layer 41b, are patterned to form the interconnection wiring and the bit line.
Here, the second interlayer insulating film 22 is patterned to expose the surface of the first contact plug 31 or to allow the second interlayer insulating film 22 to be partially left over.
Next, nitride is deposited on the entire surface of the resultant structure to form a second etching stopper film 12, and an oxide film 24 is then deposited on the entire surface of the second etching stopper film 12 and planarized by a CMP process, thereby forming a third interlayer insulating film 23.
Subsequently, the second interlayer insulating film 22, the second etching stopper film 12 and the third interlayer insulating film 23 on the memory cell region B, are selectively removed to form a second contact plug 42 on the first contact plug 31.
Thereafter, a conductive material for a dielectric film and a conductive material for an upper electrode are sequentially deposited on the resultant structure, and then patterned to form a dielectric film 45 and an upper electrode 47.
Subsequently, an interlayer insulating film 49 is formed on the resultant structure, thereby completing a semiconductor device.
As described above, in the conventional semiconductor device manufacturing method, a step difference between the memory cell region B and the logic circuit region A adjacent thereto becomes severe.
Also, in the logic circuit region A formed in the vicinity of a capacitor, the line width of a wiring is reduced and the wiring space becomes narrower in accordance with high integration of a semiconductor device.
In order to increase the integration density, as the wiring is formed in multiple layers, the number of interconnection wirings for electrically connecting the multi-layered wiring increases.
While it is necessary to more accurately form patterns in the logic circuit region A for attaining high integration, the step difference caused by a capacitor becomes gradually severe. Thus, it is quite difficult to pattern layers formed after forming the capacitor, e.g., interconnection wirings.
In other words, according to the conventional method for forming a stacked capacitor, a large step difference between a memory cell region and a logic circuit region adjacent thereto makes it difficult to achieve fine interconnection wirings formed after forming the stacked capacitor. Also, the large step difference makes it difficult to form multi-layered interconnection wirings in the logic circuit region.
To solve the above problems, it is an object of the present invention to provide a method of manufacturing a semiconductor device, which can reduce a step difference between a memory cell region and a logic circuit region adjacent thereto.
It is another object of the present invention to provide a method of manufacturing a semiconductor device, which can attain fineness of interconnection wirings by simply forming multi-layered interconnection wirings. Accordingly, to achieve the first object, there is provided a method of manufacturing a semiconductor device having a logic circuit region, a transistor having a gate electrode, and source/drain electrodes, and a memory cell region having a stacked capacitor structure, the method including the steps of a first step of forming a first contact plug connected to the drain electrode, and forming a bit line connected to the source electrode and a first interconnection wiring connected to the respective electrodes in the logic circuit region, a second step of forming a second contact plug connected to the first contact plug, a third step of flatly forming an interlayer insulating film over the resultant structure having the second contact plug, a fourth step of forming a contact partially exposing an the upper portion of the first interconnection wiring by partially removing the interlayer insulating film, and forming a second interconnection wiring by filling up the contact with a conductive material, a fifth step of producing a space where a stacked capacitor is to be formed, by selectively removing a portion of the interlayer insulating film in the memory cell region, forming a charge preservation electrode on the side wall of the interlayer insulating film, and then removing the portion of the interlayer insulating film in the memory cell, a sixth step of forming a dielectric film and an upper electrode on the charge preservation electrode, and a seventh step of flatly forming an interlayer insulating film on the resultant structure.
To achieve the second object, there is provided a method of manufacturing a semiconductor device having a logic circuit region, a transistor having a gate electrode, and source/drain electrodes, and a memory cell region having a stacked capacitor structure, the method including the steps of a first step of forming a first contact plug connected to the drain electrode, and forming a bit line connected to the source electrode and a first interconnection wiring connected to the respective electrodes in the logic circuit region, a second step of forming a second contact plug connected to the first contact plug, a third step of flatly forming an interlayer insulating film over the resultant structure having the second contact plug, a fourth step of producing a space where a stacked capacitor is to be formed, by selectively removing a portion of the interlayer insulating film in the memory cell region, forming a charge preservation electrode on the side wall of the interlayer insulating film, and then removing the portion of the interlayer insulating film in the memory cell, a fifth step of forming a dielectric film and an upper electrode on the charge preservation electrode, and a sixth step of flatly forming an interlayer insulating film on the resultant structure.